1. Field of the Invention
The present invention relates to an improved solid state image sensor.
2. Background of the Related Art
In a general solid state image sensor, a signal generated by the light incident on the photodiodes is transferred to an output through charge coupled devices. The light sensed by multiple photodiodes results in an image. Such a solid stage image sensor is smaller and lighter than a conventional CRT and has a lower driving voltage and superior durability. Moreover, imaging from the visible region to infrared region is possible, so that it is widely used in cameras employing VTRs, cameras for surveillance, office appliances and medical appliances. With the development of the semiconductor fabricating technique such solid state image sensors are able to have higher pixel densities and be further miniaturized.
Solid state image sensors use two transfer methods: an interline (IT) transfer method and a frame interline (FIT) transfer method. In the IT transfer method, a signal generated in the photodiodes is directly transferred to a vertical transfer charge coupled device (referred to as a VCCD hereinafter) for output. In the FIT transfer method, a signal generated in each photodiode is also transferred and stored to a storing location and then subsequently output.
In known solid state image sensors, using the FIT transfer method, several problems may occur when increasing the transfer clock frequencies, which is necessary when the number of pixels is increased to obtain a higher resolution. In addition, the area of the photodiode itself should be enlarged or a dark current of the device should be reduced to obtain a high definition. However, implementing each of these has not been practical.
FIG. 1A is a partial plan view of a conventional solid state image sensor portion employing the FIT transfer method.
A plurality of photodiodes 11 are formed on the semiconductor substrate in a regularly spaced matrix. Metal wires 12, to which a clock signal is applied, are formed vertically between each photodiode 11. Gate conductors (or buffers) 13, made of a polysilicon, are formed underneath metal wires 12. First and second gates 14 and 15, made of polysilicon, are formed in an overlapped arrangement with insulating layers therebetween. The overlapping protruding ends occur near the contact holes associated with gate conductors 13, with the line of overlap transverse to the metal wires 12.
FIG. 1B is a cross-sectional view taken along the line of A--A of FIG. 1A.
A first well 22 of P-type impurities is formed to a predetermined depth within an N-type silicon semiconductor substrate 21. VCCDs 24 of N-type impurities are formed on the upper surface of the second well 23, and transfer gates 25 of highly doped P-type impurities are formed, being contacted one side by VCCDs 24 and the second well 23. The N-type photodiodes 11 are formed in contact with the other side of the transfer gate 25. Photodiode upper layer 26 contains highly doped P-type impurities in order to prevent the occurrence of dark current effects. The photodiodes 11 are separated from the adjacent VCCDs 24 by a channel separating layer 27 formed of highly doped P-type impurities. Over the entire surface of the above-mentioned structure a first insulating layer 28 is formed.
First gates 14 of polysilicon are formed on the surface of the first insulating layer 28 over the VCCD 24 and the transfer gate 25. A second insulating layer 30, made of insulating material such as SiO.sub.2, is made to overlap the side and the upper surface of the first gate 14. First gate conductors (or buffers) 13, made of polysilicon, are formed on the second insulating layer 30. A first contact hole 16 connects each first gate conductor 13 to the first gate 14. A third insulating layer 31, formed of an insulating material such as SiO.sub.2, covers the first gate conductors 13. Metal wires 12, made of a conductive material such as A1 and W, are formed on the third insulating layer 31. The metal wires 12 also serve as a photo blocking layer for preventing the light from reaching portions other than the photodiodes 11. A second contact hole 17 is formed to electrically connect the metal wire 12 to the first gate conductors 13.
FIG. 1C is a cross-sectional view taken along the line B--B of FIG. 1A. FIG. 1C illustrates that first gates 14 are formed on the first insulating layer 28 in a regular spaced pattern. Second gates 15 are formed between the first gates 14 and the ends of the second gates 15 overlap with the ends of the first gates. The first and second insulating layers 28 and 30 insulate the overlapped portion of the first and the second gates.
Operation of the above described solid state image sensor is explained hereinbelow. The charges generated by the light incident on the photodiodes 11 are simultaneously transferred to VCCDs 24 via the transfer gate 25. A clocked pulse voltage is applied to the metal wire 12. The pulse voltage is supplied via the first gate conductors 13 to the first gates 14. Second gates 15 can also be pulsed with a second pulse voltage. By appropriately clocking the first and second gates 14 and 15, there is created the appropriate potential wells needed for the signal charges to be sequentially transferred down the VCCD. The transferred signal charges are then sequentially transferred into the storage location connected to one end of the VCCD 24, and then output at an output means.
Although the above described solid state image sensor uses the FIT transfer method, it still suffers from smear phenomenon because light blocking is not efficiently accomplished. Also, since the frequency of the clock signals applied to the VCCD are high and different clocks are required, the system is complicated and expensive to manufacture. Moreover, skewed clock signaling occurs because the resistance of the gate conductors formed of polysilicon is high, resulting in the occurrence of phase differences between the signal image in the central part and the peripheral part of the solid state image sensor.